• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.
    公开号:SU1637672A3
    申请号:SU4355584
    申请日:1988-03-23
    公开日:1991-03-23
    发明作者:Эшбери Хит Честер；Майкл Джексон Кевин；Эдмонд Джудис Дэррил；Ратан Пестоньи Хошан
    申请人:Интернэшнл Бизнес Машинз.Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to computer systems with interrupt controllers and, in particular, to more efficient systems that are able to transform and respond to software interrupt commands that are normally incompatible with the system.
    The purpose of the invention is to expand the scope of application due to the possibility of converting computer command mode.
    Figure 1 shows the structural scheme of the proposed computer system; 2 and 3, respectively, the format of a typical initialization command word and a work command word used to program the block.
    the interrupt processing performed on the chip 8259AJ in FIG. 4 is the structure of the decryption unit and the bidirectional key; in FIG. 5, the time diagram of the write and read cycles.
    The computer system comprises a processor 1, an interrupt processing unit 2, a common highway 3 including buses 4 and 5, respectively, addresses and data, a group of input / output blocks 6-8, a decryption block 9, a memory block 10, a permanent memory block 11, bidirectional key 12, outputs 13-15 of decryption unit 9, bus 16 for interrupt requests of I / O blocks 6-8 and bus 17 for interrupt request.
    About 00 SI
    oe 1
    YU
     04
    Bloc 9 decryption and bidirectional key 12 contain a control bus including IOW 18 and IOR 19 lines; decoder address 20, ele. cops OR 21, AND 22, NOT 23, AND-NOT 24 and 25, main elements 26 and 27, resistor 28,
    The system works as follows.
    Interrupt handling unit 2 processes up to eight vector priority interrupts for processor 1 via eight lines: IRQ, IR1, IR2, etc. to IR7, via bus 16. Only three I / O blocks 6–8 are shown connected to the system (FIG. 1) via the IRQ, IR1 and IR2 lines.
    Block 2 acts as a general manager. It accepts requests from I / O units, determines which of the incoming requests has the highest priority, checks whether the incoming request has a higher priority value than the currently serviced request, and issues an interrupt on line 17 to processor 1 on based on collected facts.
    Each I / O unit typically has a special program or procedure that is associated with its specific functional or operational requirements, which is called a service procedure. The interrupt handling unit 2, by submitting the interrupt to the processor, provides it with information that configures the software counter for the servicing procedure associated with the requesting device. This setting is the address in the vector table and is commonly referred to as vector data.
    The programmer has a choice of priority modes, allowing to create such a method of processing requests of the interrupt handling unit 2, which satisfies the requirements of the system. Priority modes can be replaced and reconfigured dynamically at any time during the main program. Therefore, it is possible to determine the interrupt structure properly.
    Programming 8259A (block 2 interrupt handling).
    Block 2 receives two types of command words generated by processor 1.
    0
    five
    0 5
    0
    0
    five
    0
    ICW is the initialization command word. The ICW1 format is shown in FIG. Before starting normal operation, unit 2 must be tuned to a starting point by a sequence of 2–4 bytes that are being activated by WP pulses.
    OCW is the work team word. The OCW1 format is shown in FIG. These are the command words that cause the 8259A to work in different interrupt modes.
    Their list is as follows: fully nested mode t reverses priority mode, special mask mode, selective mode.
    OCW words can be written to 8259A at any time after initialization.
    When a command is issued with and, it is interpreted as cVio- in initialization command 1 (ICW1) (FIG. 2). The word ICW1 begins an initialization sequence during which the following automatically occurs.
    The front-sensitive circuit is set to zero, which means that after initialization at the interrupt request input (IR), a transition from a low to a high level must occur in order for an interrupt to occur.
    The interrupt mask register is cleared.
    IR7 is assigned priority level 7.
    7 is added to the dependent mode address.
    The special mask mode is cleared and the read state is set to IRR,
    If, then all functions selected on ICW4 are set to zero.
    The modes triggered by the front and the level are programmed with the help of bit 3 of the word 1 S1 (Fig. 2).
    If LTIM O, the interrupt request is recognized as a transition from low to high level at the IR input. The IR input may remain high, not generating another interrupt. t
    If LTIM is 1, the interrupt request is recognized as high at the IR input, and there is no need for edge detection. The interrupt request must be cleared before an E01 command is issued or interrupt enabled by processor 1 to prevent a secondary interrupt.
    The computer system (Fig. 1) is designed to work normally; with software, similar to application programs, which, during initialization, issue interrupt-related instructions (ICW1), which initially set the level-sensitive mode for unit 2. It is desirable to keep the interrupt handling unit 2 at such a level-sensitive mode in order to improve performance and reduce noise problems, which lead to false recognition of the interrupt. However, when this is done, software that sends signals to front-sensitive commands, like the word ICW1 of the front mode, is. initialization times are incompatible. If the interrupt service unit 2 is a program part of the enabling logic to perform the decoding.
    4 shows the data buffer
    e which supplies data to block 2. Block 2 may consist of several BIS 8259A, with one of them being properly switched during operation. The result of the decoder 15 is
    It is either a Write Gate signal or a Read Gate signal from decoding unit 9. The Read Gate signal arriving at trunk 26 controls the write operations requiring intervention by interrupt handling unit 2. The Write Gate signal, applied to the trunk element 27, controls read operations that require the intervention of blocks 2.
    20 When writing a control word to one of the blocks 2, the Write Gate interrupt signal on line 15 is active, excluding the writing of the ICW1 command. Without activating Write Gate during
    world front-launch mode 25 ICW1 recording time data 3 bits
    7672
    supporting logic for decoding.
    4 shows the data buffer
    e which supplies data to block 2. Block 2 may consist of several BIS 8259A, with one of them being properly switched during operation. The result of the decoder 15 is
    It is either a Write Gate signal or a Read Gate signal from decoding unit 9. The Read Gate signal arriving at trunk 26 controls the write operations requiring intervention by interrupt handling unit 2. The Write Gate signal, a post on the trunk element 27, controls read operations that require the intervention of blocks 2.
    20 When writing a command word to one of the interrupt processing units 2, the Write Gate signal on line 15 is active, except for writing the ICW1 command. Without activating Write Gate during
    software written for other computer systems, this system does not complete the interrupt sequence. Therefore, logic has been added to the system to prevent the controller from being initialized to the front-launch mode. It provides software compatibility with other systems. A system without such a means is most likely less compatible with previously created application procedures for software of personal computers.
    When the front-start command is decoded by block 9, the bidirectional key 12 captures these commands and block 2 is configured to respond as if the level-sensitive command had been received.
    Frontal start mode occurs during the first word of the initialization command (ICW1). The occurrence of this feature is recognized, the LTIM data bit for setting the output of the bidirectional key 12 connected to the input of block 2 is forced to accept a value that determines the level-sensitive mode. The logic required for this function in the bidirectional switch 12 includes trunk elements 26 and 27 with three stable states for venting two 30
    35
    40
    4S
    50
    55
    this command is kept at a high level by the load resistor. When the data bit is set to ICW1, the interrupt processing unit is set or continues to remain in the sensitive mode.
    The state and features of the various control and data lines in Writing and Reading, but in more detail for the word ICW1, is shown in FIG. Formula invented
    1. A computer system with the conversion of computer command modes, comprising a processor, an interrupt processing unit, a memory block, a fixed memory, a group of yes-output blocks, with the address output of the processor through the address bus connecting the address inputs of the memory block, fixed memory, input / output units of the group, information input of the processor output via the data bus connected to information inputs of the memory block, input output groups of the group, information output of the fixed memory, a group of equal input-output processes through Inu is connected to the control groups of control inputs output memory block, block constant na
    directional data, with a slight ti, group I / O blocks,
    0
    five
    0
    S
    0
    five
    in this command, it is held at a high level by a load resistor 28. When the data bit during the recording of ICW1, the switched interrupt handling unit 2 is set or continues to remain in the sensitive mode.
    The state and features of the various control and data lines in the Write and Read operations, but in more detail for the word ICW1, are shown in FIG. Formulas and inventions
    权利要求:
    Claims (3)
    [1]
    1. A computer system with computer command mode conversion, comprising a processor, an interrupt processing unit, a memory unit, a fixed memory unit, a group of input / output units, the processor’s output output being connected to the address inputs of the memory unit via an address bus data storage unit, group input / output units, information input / output of the processor via a data bus connected to information inputs / outputs of the memory unit, input / output units of the group, information output of the fixed memory unit, control group Processor IOs of the processor through the control bus are connected to control I / O / memory block groups, the constant output block of the interrupt processing interrupt processing unit through the control gland is connected by the input of the interrupt request requirement of the control I / O group of the data processing unit. interrupts of group I / O are connected by a group of interrupt request inputs to an interrupt processing unit, characterized in that, in order to expand the application area due to the possibility of transforming computer command mode, it contains a decryption unit and a bidirectional key, the output of which is connected to the third bit input of the group of information inputs of the interrupt processing unit, and the information input is connected to the data bus, the address, information and control inputs of the decryption block g are respectively connected to the bus addresses, the data bus and the control bus, the outputs of the first to the fourth decryption unit are connected respectively to the input of the selection of the interrupt processing unit, the input of the processing of the interrupt processing unit , The first and second inputs of the directional control of the bidirectional key.
    [2]
    2. The system of claim 1, that is, the root and the fact that the decryption unit contains the address decoder, two AND-NOT elements, the NOT element, the AND element, the OR element, the output of which is connected to the first input of the element And, the output of which is the fourth output
    five
    0
    five
    0
    five
    the decryption unit, the third output of which is connected to the output of the first NAND element, the first and second inputs of which are connected respectively to the outputs of the second NAND element and the NO element, whose input is connected to the IOW line of the control bus, the INTA and IOR lines of which are connected respectively, with the second input of the AND element and the first input of the OR element, the second input of which is connected to the output of the address decoder and the first output of the decryption unit, the line AO of the address bus is connected to the first input of the second NAND element, the first input of which is connected to the line s D4 data bus, the inputs of the decoder are connected with the bus address lines AO which is connected to the second output of the de {encryption.
    -
    [3]
    3. The system according to PP, 1 and 2, T is characterized by the fact that the bidirectional (the directional key contains two main elements and a resistor, the information input of the first main element is connected to the output of the second main element and is the information input of the key the output of which is connected to the output of the first trunk element, the input of the second trunk element and through a resistor to the power bus of the computer system, the first and second control inputs of the direction of transmission of the bidirectional switch are connected to the control input of the ne vvogo and second trunk elements, respectively.
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    1 1 NEEDED TITLE 1 NEEDED TITLE
    1- SINGLE 0 CASCADE MODE
    CALL ADWESS INTERVAL 1 - INTERVAL OF If 0 INTERVAL OF 8
    7 - LEVEL TRIGGERED MOTJE 0: EDGE TRIGGERED rtODE
    At -A5 OF INTERRUPT
    VEKTOR ADRESS (HCS 80/85 MOSEONLy)
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    INTERRUPT MASK 7s MASK SET 0 MASK RESET
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    + B3 (Or8UFn) YMG 5259s)
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    Compiled by M.Sorochan
    Editor I.Shmakova Tehred L.Oliynyk
    Order 828
    Circulation 412
    VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5
    Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101
    Corrector S.Cherni
    Subscription
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3938101A|1973-12-26|1976-02-10|International Business Machines Corporation|Computer system with post execution I/O emulation|
    US4127896A|1977-08-10|1978-11-28|Bunker Ramo Corporation|Bidirectional interface utilizing read-only memory, decoder and multiplexer|
    US4236204A|1978-03-13|1980-11-25|Motorola, Inc.|Instruction set modifier register|
    US4425618A|1981-11-23|1984-01-10|Bell Telephone Laboratories, Incorporated|Method and apparatus for introducing program changes in program-controlled systems|
    US4590556A|1983-01-17|1986-05-20|Tandy Corporation|Co-processor combination|
    JPH0412853B2|1984-07-25|1992-03-05|Nippon Electric Co|
    US4695945A|1985-02-28|1987-09-22|International Business Machines Corporation|Processor I/O and interrupt filters allowing a co-processor to run software unknown to the main processor|
    JP2609220B2|1985-03-15|1997-05-14|ソニー株式会社|Multi-processor system|
    US4779187A|1985-04-10|1988-10-18|Microsoft Corporation|Method and operating system for executing programs in a multi-mode microprocessor|
    JPS6228838A|1985-07-31|1987-02-06|Nec Corp|Interruption control circuit|
    JPS63141134A|1986-12-04|1988-06-13|Mitsubishi Electric Corp|Interruption controller|
    JP2001118629A|1999-10-18|2001-04-27|Jst Mfg Co Ltd|Cooling method of connector and electronic module mounted on the connector|US5101497A|1988-09-09|1992-03-31|Compaq Computer Corporation|Programmable interrupt controller|
    CA1319441C|1988-09-09|1993-06-22|Paul R. Culley|Programmable interrupt controller|
    US5412800A|1989-05-25|1995-05-02|Cirrus Logic, Inc.|System for running incompatible graphics programs|
    JPH0375937A|1989-08-18|1991-03-29|Nec Corp|Interrupt control circuit|
    GB9012950D0|1989-11-03|1990-08-01|Ibm|Programmable interrupt controller|
    US5261107A|1989-11-03|1993-11-09|International Business Machines Corp.|Programable interrupt controller|
    US5379404A|1990-03-16|1995-01-03|Motorola, Inc.|Plug code for automatically recognizing and configuring both non-microprocessor and microprocessor based radio frequency communication devices|
    CA2115210C|1993-04-21|1997-09-23|Joseph C. Andreshak|Interactive computer system recognizing spoken commands|
    US6145047A|1994-05-19|2000-11-07|Vlsi Technology Inc.|Circuit and method for converting interrupt signals from level trigger mode to edge trigger mode|
    KR100306636B1|1994-06-28|2001-11-30|피터 엔. 데트킨|PCI-ISA Interrupt Protocol Converter and Selection Mechanism|
    US5619703A|1995-06-06|1997-04-08|Cirrus Logic, Inc.|Apparatus and method for supporting multiple interrupt protocols with unequal number of interrupt request signals|
    US5848277A|1996-02-12|1998-12-08|Ford Motor Company|Method for providing both level-sensitive and edge-sensitive interrupt signals on a serial interface between a peripheral and host|
    US5740452A|1996-03-29|1998-04-14|Vlsi Technology, Inc.|System for passing Industry Standard Architecturelegacy interrupts across Peripheral Component Interconnectconnectors and methods therefor|
    US6735655B1|1999-09-29|2004-05-11|Emc Corporation|Interrupt request controller|
    US20030018842A1|2001-07-19|2003-01-23|Donald Harbin|Interrupt controller|
    JP2008257549A|2007-04-06|2008-10-23|Nec Electronics Corp|Control circuit of microcomputer, and control method|
    法律状态:
    2010-09-20| REG| Reference to a code of a succession state|Ref country code: RU Ref legal event code: MM4A Effective date: 20070324 |
    优先权:
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    US07/029,511|US4890219A|1987-03-24|1987-03-24|Mode conversion of computer commands|
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